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The Eclipse IDE is an open-source graphical environment for creating and troubleshooting different types of program code, including Java code. Because of its versatility, installing Eclipse requires a couple of different software packages. Fortunately, the Synaptic Package Manager can take care of that for us. Just start the Synaptic Package Manager (by selecting System Administration Synaptic Package Manager), then search for the eclipse-jdt package. Mark that package for installation, and Synaptic automatically installs everything that s required to develop Java applications (including the OpenJDK package, if it s not already installed). The Eclipse package is not supported by Canonical, so it doesn t appear in the standard Ubuntu repositories. You must ensure you have the universe repository selected in your Synaptic Package Manager configuration to download the Eclipse package. To do that, start the Synaptic Package Manager, then select Settings Repositories from the menu. In the Ubuntu Software tab section, ensure that the community-maintained, open-source software (universe) check box is selected. Then click the Reload toolbar button on the main page to reload the repository library information.

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electron microscope (TEM) image (Fig 35) demonstrates the ultrathin, crystalline nature of a typical SnS14(1)Se05(1) lm spun on thermally oxidized silicon, with an average lm thickness of 50 ie, only 8 10 unit cells thick ( lm thickness and chemical composition were determined using medium-energy ion scattering MEIS)31 Substantial preferred orientation is visible, with the metal chalcogenide layers oriented nominally parallel to the substrate surface (corresponding to the fringes observed in the TEM images) The high degree of solubility, the ability to decompose at relatively low temperature, and the small volume of the dissociating hydrazinium species in the current process are all presumably important factors enabling the formation of high-quality, continuous ultrathin chalcogenide lms using the spin-coating process Using a standard TFT device con guration (Fig 36a), spin-coated SnS14(1)Se05(1) channel layers have been electrically evaluated.

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31 A representative plot of drain current ID versus drain voltage VD is shown in Fig 36b as a function of the applied gate voltage VG for a TFT with a spin-coated SnS14(1)Se05(1) channel (same lm as for Fig 35) The device operates as an nchannel transistor, working in accumulation mode upon application of a positive gate bias Application of a negative gate bias depletes the channel of electrons and shuts the device off At low VD, the TFT shows typical transistor-like behavior as ID increases linearly with VD Current saturation is observed at high VD as the accumulation layer is pinched off near the drain electrode Current modulation (Ion/Ioff) and saturation regime eld-effect mobility ( sat) are calculated from the plot of ID and I1 2 versus VG (Fig 36c),45 D yielding ION/IOFF > 106 and sat = 12.

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In the previous sections, the types of damage found in n-MOS devices have been described. Four types of damage have been found: interface states, hole traps, and two types of electron traps (not counting slow states). These types of damage are intimately linked to gate current during hoi--carrier stressing. In this section, we shall show that similar damage exists for the p--channel transistors. They show the same types of damage, for the same species of charge injected. The gate currents are reversed for p-MOS compared with n-MOS, and consequently the gate voltage range for each type of damage is reversed-linking the types of damage created in p- and n-MOS stressing to the gate current species independent of whether the damage is in n-channel or p-channel transistors. Figure 6.9 shows the gate current--gate voltage spectrum. At low gate voltages, the current is electrons and large-several orders of magnitude larger than in the nchannel transistors. The reason for this is that the secondary impact-ionized electrons have a much lower barrier (3.1 eV) for injection into the oxide than do holes in n-MOS devices (4.8 eV). The current is, consequently, much larger, even if

0 cm2/V-s, respectively, for a 60 to 85 V gate sweep and VD = 85 V The linear regime mobility derived from the plots in Fig 36b is lin = 24 cm2/V-s Note that use of a thinner or higher dielectric constant gate insulator (relative to the 210-nm SiO2 layer currently used) enables signi cant reduction in the device operating voltage over that.

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